Schottky-clamped Transistor-Transistor Logic (TTL) circuits have progressed to structures that have average signal propagation delays on the order of a nano-second. Speed power product values of a few picojoules are common. It is desirable to improve the speed power product of the internal gates in an IC chip and to reduce the area so that more gates can be integrated into a single chip. For such internal gates it is further desirable to reduce the signal voltage swing. Such reduced signal swing will improve speed and at the same time will reduce noise coupling (commonly called RFI) to nearby circuitry.
In the recently developed Advanced Low-power Schottky (ALS) devices it has been found desirable to keep the gate output signal swing below about 3 volts to avoid diode breakdown in the plural emitter transistor structures in the gate input circuits. Since the typical gate power supply voltage is 5 volts, some form of signal limiting must be employed. Typically this has been accomplished by means of a series string of diodes or a resistor voltage divider. Both of these methods require extra chip area and increase the signal propagation delay.